What makes a Teensy a microcontroller as opposed ...

BurnerBoard said:

I generally wanted to understand if it is the lack of some specific piece of a Von Neuman architecture.

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Maybe I'm reading too much into this question, but it kinda sounds like an assumption that a SBC microprocessor is a superset, that it would have everything a microcontroller has, that a microcontroller is defined pretty much only by what it lacks. But the truth is both types of chips have very different designs in many ways.

Microcontrollers like Cortex M7 are designed for low latency interrupts. Some ARM instructions, like the load and store multiple registers, can take many cycles. On M7, the CPU is able to abort those instructions and then redo them after the interrupt, so they don't add extra latency. Quite a number of other design choices go into the CPU's pipeline design to achieve that low worst case latency.

Interrupt controllers also tend to have very different design. Cortex-M microcontrollers have a nested vector interrupt controller which gives a pretty much fixed functionality for a small pre-determined set of interrupts. More traditional processors have interrupt systems which are designed to be expandable with a not-determined-in-advance set of peripherals, but they usually involve the CPU doing more work in software to manage that complexity. Features to delay interrupt processing slightly, so multiple events can be handled with the overhead of only 1 operating system context switch are also common. You get more far more flexibility and throughput, but at the cost of latency. The NVIC in Cortex-M is designed to do almost all the work in hardware (with little flexibility and no expandability), so interrupt response has the lowest possible latency.

Microcontrollers typically have memory systems designed for deterministic timing. With these newer 600 MHz M7 parts, the lines are blurred slightly, because some memory is cached and external QSPI memory is quite slow for cache misses. But still, half of the internal RAM is "tightly coupled" and partitioned as either used for instructions or data. Usually most variables and code are implemented with this fast, non-cached memory which has fixed access time. On traditional microprocessors, the memory is typically DRAM which has substantial row access time but very high burst speed to read columns within a row. Operating systems like Linux implement virtual memory and write some memory out to swap media, so random memory access time is rarely but could be as long as the media access time to restore memory from swap. But L1 & L2 cache make normal microprocessors run very fast, on average. The main difference is the large variation and possibly very long latency in those unlikely cases. Normally microcontrollers are designed to have fixed or highly deterministic memory timing.

This theme is usually found throughout the design. Traditional microprocessors are designed to maximize throughput. Microcontrollers are designed to minimize latency. Often times just making something faster wins on both fronts, but in many cases there are design trade-offs where low latency comes at the cost of high throughput, and vise versa.

Maybe I'm reading too much into this question, but it kinda sounds like an assumption that a SBC microprocessor is a superset, that it would have everything a microcontroller has, that a microcontroller is defined pretty much only by what it lacks. But the truth is both types of chips have very different designs in many ways.Microcontrollers like Cortex M7 are designed for low latency interrupts. Some ARM instructions, like the load and store multiple registers, can take many cycles. On M7, the CPU is able to abort those instructions and then redo them after the interrupt, so they don't add extra latency. Quite a number of other design choices go into the CPU's pipeline design to achieve that low worst case latency.Interrupt controllers also tend to have very different design. Cortex-M microcontrollers have a nested vector interrupt controller which gives a pretty much fixed functionality for a small pre-determined set of interrupts. More traditional processors have interrupt systems which are designed to be expandable with a not-determined-in-advance set of peripherals, but they usually involve the CPU doing more work in software to manage that complexity. Features to delay interrupt processing slightly, so multiple events can be handled with the overhead of only 1 operating system context switch are also common. You get more far more flexibility and throughput, but at the cost of latency. The NVIC in Cortex-M is designed to do almost all the work in hardware (with little flexibility and no expandability), so interrupt response has the lowest possible latency.Microcontrollers typically have memory systems designed for deterministic timing. With these newer 600 MHz M7 parts, the lines are blurred slightly, because some memory is cached and external QSPI memory is quite slow for cache misses. But still, half of the internal RAM is "tightly coupled" and partitioned as either used for instructions or data. Usually most variables and code are implemented with this fast, non-cached memory which has fixed access time. On traditional microprocessors, the memory is typically DRAM which has substantial row access time but very high burst speed to read columns within a row. Operating systems like Linux implement virtual memory and write some memory out to swap media, so random memory access time is rarely but could be as long as the media access time to restore memory from swap. But L1 & L2 cache make normal microprocessors run very fast, on average. The main difference is the large variation and possibly very long latency in those unlikely cases. Normally microcontrollers are designed to have fixed or highly deterministic memory timing.This theme is usually found throughout the design. Traditional microprocessors are designed to maximize throughput. Microcontrollers are designed to minimize latency. Often times just making something faster wins on both fronts, but in many cases there are design trade-offs where low latency comes at the cost of high throughput, and vise versa.

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